| Paper: | DISPS-P4.10 | ||
| Session: | Design and Mapping Techniques | ||
| Time: | Friday, May 21, 13:00 - 15:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware, Software, and Algorithm Tradeoffs and Integration | ||
| Title: | SYSTEMATIC EXPLOITATION OF DATA PARALLELISM IN HARDWARE SYNTHESIS OF DSP APPLICATIONS | ||
| Authors: | Mainak Sen; University of Maryland, College Park | ||
| Shuvra Bhattacharyya; University of Maryland, College Park | |||
| Abstract: | In this paper, we describe an approach that we explored for low-power synthesis and optimization of digital signal, image, and video processing (DSP) applications. In particular, we consider the systematic exploitation of data parallelism across the operations of an application dataflow graph when synthesizing a dedicated hardware implementation. Data parallelism occurs commonly in DSP applications, and provides flexible opportunities to increase throughput or lower power consumption. Exploiting this parallelism in dedicated hardware implementation comes at the expense of increased resource requirements, which must be balanced carefully when applying the technique in a design tool. We propose a high level synthesis algorithm to determine the data parallelism factor for each computation, and based on the area and performance trade-off curve, design an efficient hardware representation of the dataflow graph. For performance estimation, our approach uses a cyclostatic dataflow intermediate representation of the hardware structure under synthesis. We then apply an automatic hardware generation framework to build the actual circuit. | ||
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