| Paper: | DISPS-P3.8 | ||
| Session: | High Performance DSP Architectures and Systems | ||
| Time: | Friday, May 21, 13:00 - 15:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Algorithm Transformation and Mapping Techniques | ||
| Title: | AN LDPC DECODING SCHEDULE FOR MEMORY ACCESS REDUCTION | ||
| Authors: | Kiran Gunnam; Texas A&M University | ||
| Gwan Choi; Texas A&M University | |||
| Mark Yeary; University of Oklahoma | |||
| Abstract: | Recent research efforts based on joint code-decoder design methodology have shown that it is possible to construct structured LDPC (Low Density Parity Check) codes without any performance degradation. An interesting new data independence property between the two classes of messages viz. check to bit and bit to check involved in decoding, is observed. This property is a result of the specific structuring of parity check matrix. By exploiting this property, we propose an architecture in which the computation of messages is synchronized such that each class of messages is consumed immediately by the computational unit for another class of messages. The internal memory of the check to bit units is increased in tune with the storage requirement of the check to bit messages. The separate memories for check to bit and bit to check messages are eliminated. This approach has memory savings of 75% and reduces the overall memory accesses by 66%. | ||
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