| Paper: | SPCOM-P4.8 | ||
| Session: | Iterative Decoding Algorithms and Architectures | ||
| Time: | Wednesday, May 19, 09:30 - 11:30 | ||
| Presentation: | Poster | ||
| Topic: | Signal Processing for Communications: Compression, Coding, and Modulation | ||
| Title: | EFFICIENT DSP IMPLEMENTATION OF AN LDPC DECODER | ||
| Authors: | Gottfried Lechner; Telecommunications Research Center Vienna | ||
| Jossy Sayir; Telecommunications Research Center Vienna | |||
| Markus Rupp; Technical University of Vienna | |||
| Abstract: | We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average number of required iterations. This leads to an implementation with increased throughput compared to other implementations of LDPC codes or Turbo codes. This decoder is able to decode at 5.4Mbps on a Texas Instruments TMS320C64xx DSP running at 600MHz. | ||
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