| Paper: | DISPS-P3.3 | ||
| Session: | High Performance DSP Architectures and Systems | ||
| Time: | Friday, May 21, 13:00 - 15:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | PARALLEL GLOBAL ELIMINATION ALGORITHM AND ARCHITECTURE DESIGN FOR FAST BLOCK MATCHING MOTION ESTIMATION | ||
| Authors: | Yu-Wen Huang; National Taiwan University | ||
| Chen-Han Tsai; National Taiwan University | |||
| Liang-Gee Chen; National Taiwan University | |||
| Abstract: | The critical path of the hardware for global elimination algorithm (GEA) is too long to meet the real-time constraints for high-end applications. In this paper, we propose a new parallel GEA and its corresponding architecture. By dividing candidate blocks into independent groups and finding the most probable candidates of each group in parallel, instead of sequentially searching within the whole search range, parallel design can be developed as an array of GEA processing elements with much shorter critical path. Besides, the GEA processing element is optimized to reduce 30% of the gates, and the 2-D data reuse is organized to save 80% of the SRAM bandwidth, which also reduces a lot of power. Simulation results show that our implementation can achieve real time processing of D1 30Hz video with search range as H[-64, +63.5] V[-32, +31.5] while the operating frequency is 70MHz, and the gate count is 113K. Compared with full search, our gate count is six times smaller under the same frequency, and the PSNR loss is at most 0.1-0.2dB. | ||
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