| Paper: | DISPS-L2.2 | ||
| Session: | DSP for Communication and Coding | ||
| Time: | Friday, May 21, 15:50 - 16:10 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware, Software, and Algorithm Tradeoffs and Integration | ||
| Title: | MEMORY SUB-BANKING SCHEME FOR HIGH THROUGHPUT TURBO DECODER | ||
| Authors: | Mayank Tiwari; Arizona State University | ||
| Yuming Zhu; Arizona State University | |||
| Chaitali Chakrabarti; Arizona State University | |||
| Abstract: | Turbo codes have revolutionized the world of coding theory with their superior performance. However, the implementation of these codes is both computationally and memory-intensive. Recently, the sliding window (SW) approach has been proposed as an effective means of reducing the decoding delay as well as the memory requirements of Turbo implementations. In this paper, we present a sub-banked implementation of the SW-based approach that achieves high throughput, low decoding latency and reduced memory energy consumption. Our contributions include derivation of the optimal memory sub-banked structure for different SW configurations, study of the relationship between memory size, energy consumption and decoding latency for different SW configurations and study of the effect of number of sub-banks on the throughput and decoding latency of a given SW configuration. The theoretical study has been validated by SimpleScalar for a rate 1/3 MAP decoder. | ||
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