| Paper: | DISPS-P1.3 | ||
| Session: | VLSI Algorithms and Architectures for DSP | ||
| Time: | Friday, May 21, 09:30 - 11:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Algorithm Transformation and Mapping Techniques | ||
| Title: | REGULAR MAPPING FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURES | ||
| Authors: | Frank Hannig; Universität Erlangen-Nürnberg | ||
| Hritam Dutta; Universität Erlangen-Nürnberg | |||
| Jürgen Teich; Universität Erlangen-Nürnberg | |||
| Abstract: | Similar to programmable devices such as processors or micro controllers also reconfigurable logic devices can be built as software, by programming the configuration of the device. In this paper, we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable architectures. The application areas of most of these architectures addressing computational-intensive algorithms like video and audio processing or wireless communication. Therefore, reconfigurable arrays are in direct competition with DSP processors which are traditionally used for digital signal processing. Hence, existing mapping methodologies are closely related to approaches from the DSP world. They try to employ pipelining and temporal partitioning but they do not exploit the full parallelism of a given algorithm and the computational potential of typically 2-dimensional arrays. We present a first case study for mapping regular algorithms onto reconfigurable arrays by using our design methodology which is characterized by loop parallelization in the polytope model. The case study shows that our regular mapping methodology may lead to highly efficient implementations taking the constraints of the architecture into account. | ||
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