| Paper: | 03-P1.4 (ICASSP 2003 Paper) | ||
| Session: | ICASSP 2003 Papers | ||
| Time: | Tuesday, May 18, 13:00 - 15:00 | ||
| Presentation: | Poster (ICASSP 2003 Presentation) | ||
| Topic: | ICASSP 2003 Papers: ICASSP 2003 Papers | ||
| Title: | A GENERAL DSP PROCESSOR AT THE COST OF 23 kGATES AND 1/2 A MAN-YEAR DESIGN TIME | ||
| Authors: | Eric Tell; Linköping University | ||
| Mikael Olausson; Linköping University | |||
| Dake Liu; Linköping University | |||
| Abstract: | This paper describes the design and implementation of a 16-bit fixed point DSP processor. The processor is intended as a platform for hardware accelerators and allows additional computational units and assembler instructions to be added. The I/O facilities can also be customized to the needs of a specific application. Benchmarking has shown that the processor, without any hardware accelerators, has a performance comparable to single MAC commercial DSP processors. The architecture has been successfully synthesized in a 0.13 um process, resulting in a net-list of about 23000 gates, and a clock frequency of 195 MHz, making the performance/gate count ratio very competitive. It is also small enough to integrate 100 heterogeneous processors on a chip for example for communication infrastructure applications. The complete design time, including architecture and instruction set planning, assembler, debugger, instruction set simulator, RTL code and complete verification was about half a person-year. | ||
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