| Paper: | DISPS-L1.4 | ||
| Session: | VLSI Architectures for Video and Image Processing | ||
| Time: | Wednesday, May 19, 14:00 - 14:20 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | MEMORY ANALYSIS AND ARCHITECTURE FOR TWO-DIMENSIONAL DISCRETE WAVELET TRANSFORM | ||
| Authors: | Chao-Tsung Huang; National Taiwan University | ||
| Po-Chih Tseng; National Taiwan University | |||
| Liang-Gee Chen; National Taiwan University | |||
| Abstract: | The large amount of the frame memory access and the die area occupied by the embedded internal buffer are the most critical issues for the implementation of two-dimensional discrete wavelet transform (2-D DWT). The former would consume the most power and waste the system memory bandwidth. The latter would enlarge the chip size and also consume much power. In this paper, we categorize and analyze the 2-D DWT architectures by different external memory scan methods. Then the overlapped strip-based scan method is proposed to provide an efficient and flexible implementation for 2-D DWT. The implementation issues of the internal buffer are also discussed, including the lifting-based and convolution-based. Some real-life experiments are given to show that the performance of area and power for the internal buffer is highly related to memory technology and working frequency, instead of the required memory bits only. | ||
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