| Paper: | DISPS-L1.3 | ||
| Session: | VLSI Architectures for Video and Image Processing | ||
| Time: | Wednesday, May 19, 13:40 - 14:00 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | FULLY UTILIZED AND REUSABLE ARCHITECTURE FOR FRACTIONAL MOTION ESTIMATION OF H.264/AVC | ||
| Authors: | Tung-Chien Chen; National Taiwan University | ||
| Yu-Wen Haung; National Taiwan University | |||
| Liang-Gee Chen; National Taiwan University | |||
| Abstract: | In this paper, we contributed a new VLSI architecture forfractional motion estimation of H.264/AVC. Seven inter-relatedloops extracted from complex procedure are analyzed and twodecomposing techniques are proposed to parallelize the algorithmfor hardware with regular schedule and full utilization. Theproposed architecture, also characterized by reusable feature, can support situations in different specification, multiple standards, fast algorithm and some cost considerations. H.264/AVC baseline profile Level 3 with complete Lagrangian mode decision can be realized with 270K gates at operating frequency of 100MHz. It is an useful Intellectual Property (IP) design for platform based multimedia system. | ||
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