Technical Program

Paper Detail

Paper:DISPS-L1.2
Session:VLSI Architectures for Video and Image Processing
Time:Wednesday, May 19, 13:20 - 13:40
Presentation: Lecture
Topic: Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware
Title: ENERGY EFFICIENT CLUSTER CO-PROCESSORS
Authors: Ali Ibrahim; University of Utah 
 Mike Parker; University of Utah 
 Al Davis; University of Utah 
Abstract: New 3G wireless algorithms require more performance than can be currently provided by embedded processors. ASIC implementations solve this problem but are costly and sacrifice generality. This paper introduces a new approach which organizes the execution and storage resources differently. The execution units are clustered and embedded in a richer set of communication resources. Fine grain control of these resources is imposed by a wide-word horizontal micro-code program. The advantages of this approach are quantified on a suite of six algorithms that are taken from both traditional DSP applications and from the new 3G cellular telephony domain. The result is surprising. The execution clusters retain much of the generality of a conventional processor while simultaneously improving performance by an order of magnitude and reducing power consumption by an order of magnitude when compared to a conventional embedded processor such as the Intel XScale.
 
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